1. Yuan Cao and Chip Hong Chang (Editors), ”Frontiers in Hardware Security and Trust: Theory,

Design and Practice,” IET, 2020 (Jiaji He, Xialong Guo, Yiqiang Zhao and Yier Jin, ”Chapter

5. Formal Verification for SoC Security”)

2. S. Bhunia, S. Ray, and S. Sur-Kolay (Editors), “Fundamentals of IP and SoC Security - Design,

Verification and Debug,” Springer, 2017 (Xiaolong Guo, Raj Gautam Dutta, and Yier Jin,

“Chapter 10. IP Trust Validation Using Proof-Carrying Hardware”)

3. P. Mishra, S. Bhunia, and M. Tehranipoor (Editors), “Hardware IP Security and Trust,”

Springer, 2017 (Raj Gautam Dutta, Xiaolong Guo and Yier Jin, “Chapter 4. IP Trust: The

Problem and Design/Validation-Based Solution”)

1. Zhu, Huifeng, Haoqi Shan, Dean Sullivan, Xiaolong Guo, Yier Jin, and Xuan Zhang.“PDNPulse:

Sensing PCB Anomaly with the Intrinsic Power Delivery Network.” IEEE Transactions on In-

formation Forensics and Security (TIFS), (2023).

2. Zhu, Huifeng, Xiaolong Guo, Yier Jin, and Xuan Zhang. ”PowerScout: Security-Oriented

Power Delivery Network Modeling for Side-Channel Vulnerability Analysis.” IEEE Transac-

tions on Emerging Topics in Computing (2023).

3. Kejun Chen, Orlando Arias, Xiaolong Guo, Qingxu Deng, and Yier Jin, “IP-Tag: Tag-Based

Runtime 3PIP Hardware Trojan Detection in SoC Platforms,” IEEE Transactions on Computer-

Aided Design of Integrated Circuits and Systems. 2022 May 10;42(1):68-81.

4. Zhang, Qizhi, Liang Liu, Yidong Yuan, Zhe Zhang, Jiaji He, Ya Gao, Yao Li, Xiaolong Guo,

and Yiqiang Zhao. “A Gate-Level Information Leakage Detection Framework of Sequential

Circuit Using Z3,” Electronics 11, no. 24 (2022): 4216.

5. Kejun Chen, Orlando Arias, Qingxu Deng, Daniela Oliverira, Xiaolong Guo, and Yier Jin,

“FineDIFT: Fine-Grained Dynamic Information Flow Tracking for Data-Flow Integrity using

Coprocessor,” IEEE Transactions on Information Forensics and Security (TIFS), 2022.

6. Jiaji He, Xiaolong Guo, Mark Tehranipoor, Apostol Vassilev, and Yier Jin, ”EM Side Channels

in Hardware Security: Attacks and Defenses,” IEEE Design & Test on Computers (DT), vol.

39, no. 2, pp. 100-111, 2022.

7. Jiaji He, Haocheng Ma, Max Panoff, Hanning Wang, Yiqiang Zhao, Leibo Liu, Xiaolong Guo,

and Yier Jin, “Security Oriented Design Framework for EM SideChannel Protection in RTL

Implementations,” IEEE Transactions on ComputerAided Design of Integrated Circuits and

Systems (TCAD), 2021.

8. Kejun Chen, Xiaolong Guo, Qingxu Deng, Yier Jin, “Dynamic Information Flow Tracking:

Taxonomy, Challenges, and Opportunities,” Micromachines. Special Issue Hardware Security

Attacks and Countermeasures in Integrated Circuits, 2021.

9. Qihui Yang, Chunlin Yi, Aram Vajdi, Lee W. Cohnstaedt, Hongyu Wu, Xiaolong Guo, and

Caterina M. Scoglio. “Short-term forecasts and long-term mitigation evaluations for the

COVID-19 epidemic in Hubei Province, China.” Infectious Disease Modelling 5 (2020): 563-

574.

10. Jiaji He, Xiaolong Guo, Travis Meade, Raj Gautam Dutta, Yiqiang Zhao, Yier Jin, “SoC

Interconnection Protection through Formal Verification”, in Integration, the VLSI Journal,

vol. 64, pp. 143-151, 2019.

11. Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra, Yier Jin, “Automatic Code Converter

Enhanced PCH Framework for SoC Trust Verification, ” in IEEE Transactions on Very Large

Scale Integration Systems (TVLSI), vol. 25, no. 12, pp. 3390-3400, 2017.

12. Jiaji He, Yiqiang Zhao, Xiaolong Guo, Yier Jin, “Hardware Trojan Detection through Chip-

Free Electromagnetic Side-Channel Statistical Analysis,” in IEEE Transactions on Very Large

Scale Integration System (TVLSI), vol. 25, no. 10, pp. 2939-2948, 2017.

13. Yier Jin, Xiaolong Guo, Raj Gautam Dutta, Mohammad-Mahdi Bidmeshki, Yiorgos Makris,

”Data Secrecy Protection through Information Flow Tracking in Proof-Carrying Hardware IP

Part I: Framework Fundamentals”, in IEEE Transactions on Information Forensic and Security

(TIFS), vol. 12, no. 10, pp. 2416-2429, 2017.

14. Mohammad-Mahdi Bidmeshki, Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Yiorgos Makris,

”Data Secrecy Protection through Information Flow Tracking in Proof-Carrying Hardware IP

Part II: Framework Automation”,in IEEE Transactions on Information Forensic and Security

(TIFS), vol. 12, no. 10, pp. 2430-2443, 2017.

15. Xiaolong Guo, Raj Gautam Dutta, Yier Jin, “Eliminating the Hardware-Software Boundary: A

Proof-Carrying Approach for Trust Evaluation on Computer Systems, ” in IEEE Transactions

on Information Forensic and Security (TIFS), 2016.

16. Xiaolong Guo, Shuai Yuan, “A New Tree Pruning SD Algorithm to Eliminate Interference,”

Int. J. Digital Cont. Tech. Appl., January 2013.

17. Shiliang Wang, Xiaolong Guo, M. U. M. BakuraA, Songlin Sun, Xiaojun Jing, and Hai Huang,

“A Radius Choice Algorithm For MIMO Sphere Decoding Based on the Noise Statistics,” in

Journal of Computational Information System, no. 6, vol. 8, pp. 2041-2048, 2012.

18. Jing Fu, Xiaojun Jing, and Xiaolong Guo, “CU-SURF: Colored Speeded Up Robust Features,”

in Journal of Computational Information Systems, 2012.

1. Fu, Weimin, Honggang Yu, Orlando Arias, Kaichen Yang, Yier Jin, Tuba Yavuz, and Xiaolong

Guo. ”Graph Neural Network based Hardware Trojan Detection at Intermediate Represen-

tative for SoC Platforms.” In Proceedings of the Great Lakes Symposium on VLSI 2022, pp.

481-486. 2022.

2. Zhaoxiang Liu, Orlando Arias, Weimin Fu, Yier Jin and Xiaolong Guo, “Inter-IP Malicious

Modification Detection through Static Information Flow Tracking,” Design, Automation Test

in Europe Conference Exhibition (DATE), 2022.

3. Orlando Arias, Zhaoxiang Liu, Xiaolong Guo, Yier Jin and Shuo Wang, “RTSec: Automated

RTL Code Augmentation for Hardware Security Enhancement,” Design, Automation Test in

Europe Conference Exhibition (DATE), 2022.

4. Weimin Fu, Orlando Arias, Yier Jin, and Xiaolong Guo, “Fuzzing Hardware: Faith or Reality?”

IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH), 2022.

5. Xiaolong Guo, Song Han, X. Sharon Hu, Yier Jin, Fanxin Kong, and Michael Lemmon, “To-

wards Scalable, Secure, and Smart Mission-Critical IoT Systems: Review and Vision,” Inter-

national Conference on Embedded Software (EMSOFT), 2021.

6. Yichen Jiang, Huifeng Zhu, Haoqi Shan, Xiaolong Guo, Xuan Zhang and Yier Jin, “TRRScope:

Understanding Target Row Refresh Mechanism for Modern DDR Protection,” Hardware-

Oriented Security and Trust (HOST), 2021.

7. Yichen Jiang, Huifeng Zhu, Xiaolong Guo, Xuan Zhang, Yier Jin, “Quantifying Rowhammer

Vulnerability for DRAM Security,” in 2021 IEEE Design Automation Conference (DAC).

8. Huifeng Zhu, Xiaolong Guo, Yier Jin, Xuan Zhang, “PCBench: Benchmarking of Board-

Level Hardware Attacks and Trojans,” in The 26th Asia and South Pacific Design Automation

Conference (ASP-DAC 2021). Best Paper Nominate

9. Huifeng Zhu, Xiaolong Guo, Yier Jin, and Xuan Zhang, ”PowerScout: A Security-Oriented

Power Delivery Network Modeling Framework for Cross-Domain Side-Channel Analysis,”

IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2020. Best

Paper Award

10. Qizhi Zhang, Jiaji He, Yiqiang Zhao, and Xiaolong Guo, ”A Formal Framework for Gate-

Level Information Leakage Using Z3,” IEEE Asian Hardware Oriented Security and Trust

Symposium (AsianHOST), 2020.

11. Xiaolong Guo, Huifeng Zhu, Xuan Zhang, Yier Jin, “Model-Driven Analog Vulnerabilities

Detection in the Digital Domain,” at the Workshop on Top Picks in Hardware and Embedded

Security, co-located at ICCAD 2020.

12. Jiaji He, Xiaolong Guo, Haocheng Ma, Yanjiang Liu, Yiqiang Zhao, Yier Jin, “Runtime Trust

Evaluation and Hardware Trojan Detection Using On-Chip EM Sensor,” in 2020 IEEE Design

Automation Conference (DAC).

13. Jiaji He, Haocheng Ma, Xiaolong Guo, Yiqiang Zhao, Yier Jin, “Design for EM Side-Channel

Security through Quantitative Assessment of RTL Implementations,”, in The 25th Asia and

South Pacific Design Automation Conference (ASP-DAC), 2020.

14. Kejun Chen, Qingxu Deng, Yumin Hou, Yier Jin, Xiaolong Guo, “Hardware and Software Co-

Verification from Security Perspective,” in 20th International Workshop on Microprocessor

and SOC Test and Verification (MTV), Texas, USA, December 2019.

15. Xiaolong Guo, Raj Gautam Dutta, Jiaji He, Mark M. Tehranipoor, and Yier Jin, “QIF-Verilog:

Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security

Assessment,” in IEEE International Symposium on Hardware-Oriented Security and Trust

(HOST), 2019.

16. Xiaolong Guo, Huifeng Zhu, Yier Jin, Xuan Zhang, “When Capacitors Attack: Formal Method

Driven Design and Detection of Charge-Domain Trojans,” Design, Automation Test in Europe

Conference Exhibition (DATE), 2019. Best Paper Award

17. Xiaolong Guo, Jiaji He, and Yier Jin, “Runtime SoC Trust Verification using Integrated Sym-

bolic Execution and Solver,” Government Microcircuit Applications and Critical Technology

Conference (GOMACTech-18), 2018.

18. Jiaji He, Xiaolong Guo, and Yier Jin, “Golden Chip Free Electromagnetic Simulation and

Statistical Analysis for Hardware Security,” Government Microcircuit Applications and Critical

Technology Conference (GOMACTech-18), 2018.

19. Xiaolong Guo, Raj Gautam Dutta, Jiaji He, and Yier Jin, “PCH Framework for IP Runtime

Security Verification,” Asian Hardware Oriented Security and Trust (AsianHOST), 2017.

20. Raj Gautam Dutta, Xiaolong Guo and Yier Jin, “Estimation of Safe States of Autonomous

System Under Attack,” in 2017 IEEE Design Automation Conference (DAC), Austin, TX,

USA, June, 2017.

21. Xiaolong Guo, Raj Gautam Dutta, and Yier Jin, “Proof-Carrying Hardware based IP Pro-

tection,” in Government Microcircuit Applications and Critical Technology Conference (GO-

MACTech), 2017.

22. Raj Gautam Dutta, Xiaolong Guo and Yier Jin, “Trusted Autonomous Systems under Sen-

sor Attacks,” in Government Microcircuit Applications and Critical Technology Conference

(GOMACTech), 2017.

23. Xiaolong Guo, Raj Gautam Dutta, Yier Jin “Symbolic Algebra Based Proof-Carrying ASIC,”

in 17th International Workshop on Microprocessor and SOC Test and Verification (MTV),

Texas, USA, December 2016.

24. Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra, Mark Tehranipoor and Yier Jin, “Scalable

SoC Trust Verification Using Integrated Theorem Proving and Model Checking,” in IEEE

International Symposium on Hardware-Oriented Security and Trust (HOST), 2016.

25. 24. Raj Gautam Dutta, Xiaolong Guo and Yier Jin, “Quantifying Trust in Autonomous System

Under Uncertainties,” in IEEE SoC (System-on-Chip) Conference (SOCC), 2016.

26. Xiaolong Guo, Raj Gautam Dutta, Yier Jin, “Hierarchy-Preserving Formal Verification Meth-

ods for Pre-Silicon Security Assurance,” in 16th International Workshop on Microprocessor

and SOC Test and Verification (MTV), Texas, USA, December 2015.

27. Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Fariman Farahmandi, Prabhat Mishra, “Pre-

Silicon Security Verification and Validation: A Formal Perspective,” in 2015 IEEE Design

Automation Conference (DAC), CA, USA, June 2015.

28. Xiaolong Guo, Songlin Sun, Xiaojun Jing, Hai Huang, “A Stable Expected Complexity Sphere

Detection with IRA Enhancement,” in Proc. IEEE Vehi. Tech. Conf. (VTC), Dresden,

Germany, June. 2013.

29. S. Wang, Xiaolong Guo, Songlin Sun, Tiehong Tian, and Xiaojun Jing, “A Tree Pruning

Algorithm For MIMO Sphere Decoding Based On Path Metric,” in Proc. IEEE 75th Vehi.

Tech. Conf. (VTC), Spring, 2012.

30. Xiaolong Guo, Yanhong Ju, Songlin Sun, “Improvement of the MIMO Detection Through a

Hierarchical K-Best OSIC-SE System,” in IET International Conference on Communication

Technology and Application (ICCTA 2011), pp. 181-186, 2011.